| |
Test Conditions |
Min |
Typ |
Max |
Unit |
Duty Cycle:
TTL @ 1.4V, 4.5-5.5V
|
< 50 MHz, CL = 50 pF
50-66 MHz, CL = 15 pF
66-125 MHz, CL = 25 pF
125-133 MHz CL = 15 pF
|
45
45
40
40 |
|
55
55
60
60 |
%
%
%
% |
Duty Cycle:
CMOS @ VDD/2
4.5-5.5VDD
3.0-3.6VDD
|
< 66 MHz, CL <
25 pF
66-125 MHz, CL < 25 pF
125-133 MHz CL < 15 pF
< 40 MHz, CL < 35 pF
40-100 MHz CL < 15 pF |
45
40
40
45
40 |
|
55
60
60
55
60 |
%
%
%
%
% |
Output Clock Rise/Fall
|
0.8V-2.0V, 4.5-5.5VDD, CL
= 50 pF
0.8V-2.0V, 4.5-5.5VDD, CL =
25 pF
0.8V-2.0V, 4.5-5.5VDD, CL =
15 pF
0.2-0.8VDD, 4.5-5.5VDD, CL
= 50 pF
0.2-0.8VDD, 3.0-3.6VDD, CL
= 30 pF
0.2-0.8VDD, 3.0-3.6VDD, CL
= 15 pF |
|
|
1.8
1.2
0.9
3.4
4.0
2.4 |
ns
ns
ns
ns
ns
ns |
| Start Up Time |
From power on |
|
|
10 |
ms |
Power Down Delay Time
Synchronous
Asynchronous |
PWR DWN pin HIGH to output Low
|
|
T/2
10 |
T+10
15 |
ns
ns |
Output Disable Time
Synchronous
Asynchronous |
OE pin HIGH to output Hi-Z
T=Frequency Oscillator period
|
|
T/2
10 |
T+10
15 |
ns
ns |
| Output Enable Time |
|
|
|
100 |
ns |
Power Supply Current:
(unloaded) |
4.5-5.5V VDD, Output FREQ
<133 MHz
3.0-3.6V VDD, Output FREQ <100
MHz
2.5-3.0V VDD, Output FREQ <66
MHz |
|
|
45
25
20 |
mA
mA
mA |
| Period Jitter:
∑ |
1 - 133 MHz |
|
8 |
11 |
ps |
| Peak to Peak |
< 33.000, 5V
> 33.000, 5V |
|
65
65 |
99
80 |
ps
ps |
|
